Integrate VDT into the RTL synthesis #560
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I implemented some additions/improvements discussed with @linushdot this week:
Imho this is ready to merge now. Next steps should be to integrate the Risc-V Suite + an Analysis/Evaluation Pipeline into our existing automated Docker-Based tests runners. |
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The code looks good to me as well.
I confirmed that the test suite works on rv32i with the different versions of the decoder in it.
I also tried to prove equivalence of the decoders with Yosys. The new decoders are equivalent. But I ran into difficulties comparing the new decoders to the old implementation. We can very likely disregard that, since the new decoders pass the test suite as well and provider better implementations for the decoder. Or it even means that old decoder was not correct.
- Implement generator to represent the decision logic of the decode tree as a Chisel module
- For fixed-length, non-overlapping instruction sets, we may use Chisel's truth/decoder table with circuit optimizations to generate a decoder
- add decoder option for the RTL table based decoder - improve the RTL template formatting
- improve structure of the hdl decision tree by moving default assignments to the top - for now use big-endian byte order to be compatible with the existing RTL description - Always decode/match all ISA instructions, even if no output signal depends on them (as we don't want to fall back to 'invalid' in this case) - Fix/run the test suite (locally) with all 3 decoder versions and the rv43im spec. - Use wildcards in the rtl-table output patterns
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Changes introduced within this PR:
rtl-tableto optionally select table-based decoder